The transfer of data between cards on a backplane is often required in a digital system design. Transferring data by way of a serial communications channel makes greater use of the available resources, such as the number of pins used to transfer data. For example, a system processing 64 bits of data at 80 MHz can use a 64-bit data link to another circuit or across a backplane. This same data can be transmitted serially over 16 lines single data rate (SDR) at 320 MHz, producing a 75% pin savings. Alternatively, the data can be serialized to eight differential pairs (i.e. still using 16 lines) running at 320 MHz double data rate (DDR) (640 Mb/s). This also produces a pin savings of 75% with greater signal integrity and lower power. However, one important factor in transmitting serial data is to enable the clock and data recovery circuitry to operate effectively.
A system designer providing low speed signals and single ended signals must consider signal undershoot and overshoot in order to maximize the signal integrity. However, high speed signals and differential signals provided in serial data communication require a different type of optimization. The “eye diagram” of the received signal, which may only be a few millivolts, must be optimized for “openness” in order for the clock and data recovery circuitry to operate effectively. The openness of the eye diagram is affected by a number of factors, such as signaling speed, transmission media (e.g. cable type, printed circuit board substrate material, transmission length, etc.), transmitter pre-emphasis, receiver equalization, transmission line type (e.g. microstrip, stripline, buried microstrip, simple stackup, cable type, etc.). However, some of these factors may not be known to the system designer in advance, and/or may change over time.
The optimization of the eye diagram of a received signal may be accomplished through the use of expensive simulation tools that simulate the received signal at the input pins of the receiver. However, such a simulation would require the system designer to consider all possible transmission scenarios, and determine the proper channel optimization settings for each scenario in advance. For example, if a backplane transmission media is used, the system designer would have to consider all possible combinations of transmitter and receiver slots, as well as the different lengths, or types of transmission cable.
Accordingly, this analysis would be a considerable burden for the system designer. Further, while the system designer would prefer to optimize the channel characteristics inside the clock/data recovery circuit, the system designer does not have visibility internal to the receiver.
Accordingly, there is a need for an improved circuit for transmitting serial data and method of optimizing the transmission of data on a serial communication channel.